1. Field of the Invention
This invention relates to automation of logic circuit design using a computer and particularly to a gated clock design supporting system intended to reduce load of procedure for clock gating in the design of a gated clock.
2. Description of the Related Art
Recently, semiconductor chips like LSI have tended to be highly integrated and enlarged, so that power consumption also has simultaneously increased. The gated clock design method has been developed to generate a logic circuit having a small power consumption.
Here, the aforementioned gated clock deign will be described simply. In a subsequent description, the changing of the logic circuit by the gated clock design is referred to as clock gating.
FIG. 1 is a partial circuit diagram showing a part of a synchronous logic circuit to be subjected to logic design, indicating a logic circuit not clock-gated. In the same Figure, FF0, FF1, . . . FF31 indicate D flip-flops and a 32-bit register is formed of 32 flip-flops. A clock signal is supplied to clock input port (CK) of each flip-flop at the same timing and data calculated in data operating circuit 11 is written through data input port D at the same timing as the rise of the clock signal. It has been known that in such a logic circuit, a large amount of power is consumed when the flip-flop is actuated at a rise and fall of the clock. However, because the clock signal is inputted to the flip-flop always at a constant time frame, wasted power is wasted when data fetch is not required.
FIG. 2 is a circuit structure diagram of a clock-gated logic circuit, indicating an example in which an AND gate 12 is inserted on a clock line of FIG. 1 as a gating circuit. An enable logic circuit (not shown) for controlling clock output is connected to this AND gate 12, so that enable logic output of "1" or "0" is supplied from the enable logic circuit to the AND gate 12 corresponding to a timing of the clock signal.
In FIG. 2, when the enable logic output is set to "1", data write is carried out because AND is established when the clock signal rises. On the other hand, if the enable logic output is set to "0", data write is not carried out because AND is not established even if the clock signal rises. When data write is not required, it is possible to prevent consumption of waste power at the flip-flops by making enable logic output to be "0" corresponding to clock timing.
In the aforementioned gated clock design, enable logic circuit for clock gating must be added to the logic circuit at a logical design stage. However, according to the prior art, addition and correction of description in an enable logic circuit in a net list describing a composition of the logic circuit are carried out manually by a designer. Thus, it takes much labor and time when the list is modified and there is a fear that a correction error may occur. Further, for an added enable logic circuit to operate normally in a logic circuit, an enable logic portion needs to satisfy an independent timing constraint different from a data transfer portion. However, this timing constraint differs depending on a method for clock gating, for example, which of the AND gate or OR gate is used in the gating circuit. Therefore, the designer must produce a complicated timing constraint to be supplied to a design supporting CAD.
As described above, in the prior art gated clock design, it takes much labor and time for correction of a list or calculation for timing constraint when an enable logic circuit is added. Further, if a correction error or calculation error occurs, the same work must be repeated, so that it takes further time.